The ability to perform and achieve high speed transmissions of digital data has become expected in today's computing environment. In most cases, the transmission of digital data over longer distances is accomplished by sending the data in a high-speed serial format (i.e., one single bit after another) over a communication link designed to handle computer communications. In this fashion, data can be transferred from one computer system to another, even if the computer systems are geographically remote.
In order for high-speed serial transmission to occur, the digital data signal from inside the computer must be transformed from the parallel format into a serial format prior to transmission of the data over the serial communication link. This transformation is generally accomplished by processing the computer's internal data signal through a piece of computer equipment known as a serial link transmitter or “serializer”. The function of the serializer is to receive a parallel data stream as input and, by manipulating the parallel data stream, output a serial form of the data capable of high-speed transmission over a suitable communication link. Once the serialized data has arrived at the desired destination, a piece of computer equipment known as a “deserializer” is employed to convert the incoming data from the serial format to a parallel format for use within the destination computer system.
For high speed serializer/deserializer (HSS) link pairs, a phase-locked loop (PLL) is used to get a phase lock based on the incoming signal. A basic block diagram of a typical PLL is illustrated in FIG. 1. The PLL includes a phase/frequency detector (PD) 10 coupled to a charge pump (CP) 12, which is coupled to a voltage controlled oscillator (VCO) 14. A regulator (REG) 16 is included for the PLL circuitry to supply a filtered/regulated version of the supply voltage (Vcc) to the VCO 14. The PD 10 compares the phase (FREQout) of the VCO 14 signal filtered through a frequency divider (DIV) 18 with that of the incoming signal (FREQin) and adjusts the control voltage (Vcntrl) to keep the VCO 14 in phase with the incoming signal.
In general, maintaining the control voltage of the VCO within a certain range helps in reducing jitter. Prior art approaches have designed the VCO/control voltage with a fixed high gain to cover the range. In an alternative design, the regulator output voltage can be set to set the power supply voltage that the VCO sees. While such approaches do address the jitter problem to a certain extent, they are limited against having the flexibility to more readily address jitter across a broad range of variations in the incoming signal frequency.
Accordingly, a need exists for a manner of reducing jitter in PLLs of high speed serial links that accommodates variations in the incoming signal frequency. The present invention addresses such a need.